
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   10:24:07 09/18/2007
-- Design Name:   top
-- Module Name:   G:/mprj/xiltendo/VQ44_uart/tb_uart.vhd
-- Project Name:  VQ44_uart
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: top
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_uart_vhd IS
END tb_uart_vhd;

ARCHITECTURE behavior OF tb_uart_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT top
	PORT(
		PHI : IN std_logic;
		CS : IN std_logic;
		RD : IN std_logic;
		WR : IN std_logic;    
		AD : INOUT std_logic_vector(7 downto 0);
		XA : INOUT std_logic_vector(5 downto 0);
		XB : INOUT std_logic_vector(5 downto 0);
		VCCB : INOUT std_logic;      
		REQ : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL PHI :  std_logic := '0';
	SIGNAL CS :  std_logic := '1';
	SIGNAL RD :  std_logic := '1';
	SIGNAL WR :  std_logic := '1';

	--BiDirs
	SIGNAL AD :  std_logic_vector(7 downto 0);
	SIGNAL XA :  std_logic_vector(5 downto 0);
	SIGNAL XB :  std_logic_vector(5 downto 0);
	SIGNAL VCCB :  std_logic;

	--Outputs
	SIGNAL REQ :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: top PORT MAP(
		PHI => PHI,
		CS => CS,
		RD => RD,
		WR => WR,
		REQ => REQ,
		AD => AD,
		XA => XA,
		XB => XB,
		VCCB => VCCB
	);

	-- 4.19 MHZ
	tbc : PROCESS
	BEGIN
		PHI <= '1'; wait for 119 ns;
		PHI <= '0'; wait for 119 ns;
	END PROCESS;


	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 405 ns;

		-- Place stimulus here
		AD <= X"8C"; wait for 2 ns;
		
		WR <= '0'; wait for 2 ns;
		WR <= '1'; wait for 2 ns;
		
		AD <= "ZZZZZZZZ"; wait for 2 ns;
		CS <= '0';
		RD <= '0';


		wait; -- will wait forever
	END PROCESS;

END;
